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ds06-20112-2e fujitsu semiconductor data sheet copyright?2002-2007 fujitsu limited all rights reserved semicustom cmos embedded array CE77 series description the CE77 series 0.25 m cmos embedded array is a line of highly integrated cmos asics featuring high speed and low power consumption at the same time. CE77 series is available in 15 frames wi th the enhanced lineup of 470 k to 6980 k gates. features ? technology : 0.25 m silicon-gate cmos, 3- to 4-layer wiring supply voltage : + 2.5 v 0.2 v (normal) to + 1.5 v 0.1 v junction temperature range : ? 40 c to + 125 c gate delay time : t pd = 33 ps (2.5 v, inverter cell high speed type, f/o = 1, no load) gate power consumption : 0.02 w/mhz (1.5 v, f/o = 1, no load) high-load driving capability : i ol = 2 ma/4 ma/8 ma/12 ma mixable output buffer cells with noise reduction circuits inputs with on-chip input pull-up/pull-down resistors (25 k ? typical) and bidirectional buffer cells buffer cells dedicated to crystal oscillator special interface (p-cml, lvds, t-lvttl, sstl, pci, usb, gtl + , and others including those under development) ip macros (cpu, pci, usb, irda, pll, dac, adc, and others including those under development) capable of incorporating compiled cells (ram/rom/fifo/delay line, and others.) configurable internal bus circuits advanced hardware/software co-design environment support for static timing sign-off dramatically reducing the time for generating test ve ctors for timing verification and the simulation time hierarchical design environment for supporting large-scale circuits simulation (before layout) considering the input slew ra te and detailed rc delay calculation (after layout) , supporting development with minimized ti ming trouble after trial manufacture (continued)
CE77 series 2 (continued) support for memory (ram/rom) scan support for memory (ram) bist support for boundary scan support for path delay test a variety of package options (sqfp, hqfp, pbga, lqfp, fbga under development) macro library (including macros being prepared) 1. logic cells (about 700 types) 2. ip macros 3. special i/o interface macros adder and-or and-or inverter decoder clock buffer non-scan flip flop latch inverter nand buffer and or-and inverter nor or scan flip flop selector bus driver enor eor boundary scan register others cpu sparclite, arm7 interface macro usb, irda, etc. multimedia processing macros jpeg, etc. mixed signal macros adc, dac, analog switch, etc. compiled macros ram, ro m, fifo, delay line, pll analog pll p-cml usb
CE77 series 3 chip structure the chip layout of the CE77 seri es consists of two major areas : chip peripheral area and basic cell area. the chip peripheral area contains the input/output buffer cells for interfacing with external devices and the associated bonding pads. the basic cell area contains some of input/o utput buffer cells, the unit cells and the compiled cells. chip configuration bonding pad i/o buffer cell basic cell area
CE77 series 4 compiled cells compiled cells are macro cells which are automatically gener ated with the bit/word co nfiguration specified. the CE77 series has the following types of compiled cells (note that each macro is different in word/bit range depending on the column type) . 1. clock synchronous single-port ram (1 address, 1 rw) (high density type) / (partial write type) (ultra high density type) (low power consumption type) (high speed type) 2. clock synchronous dual-port ram (2 addresses, 1 rw/1 r) 3. clock synchronous register file (3 addresses, 1w/2r) 4. clock synchronous register file (4 addresses, 2w/2r) column type memory capacity word range bit range unit 4 16 to 72 k 16 to 1 k 1 to 72 bit 16 64 to 72 k 64 to 4 k 1 to 18 bit column type memory capacity word range bit range unit 4 64 to 72 k 32 to 1 k 2 to 72 bit 4 2064 to 512 k 1032 to 4 k 2 to 128 bit 16 4160 to 512 k 2080 to 16 k 2 to 32 bit column type memory capacity word range bit range unit 4 128 to 72 k 32 to 1 k 4 to 72 bit 8 256 to 72 k 64 to 2 k 4 to 36 bit column type memory capacity word range bit range unit 8 128 to 144 k 32 to 2 k 4 to 72 bit column type memory capacity word range bit range unit 4 16 to 72 k 16 to 1 k 1 to 72 bit 16 64 to 72 k 64 to 4 k 1 to 18 bit column type memory capacity word range bit range unit 1 4608 4 to 64 1 to 72 bit column type memory capacity word range bit range unit 1 4608 4 to 64 1 to 72 bit
CE77 series 5 5. clock synchronous rom (1 address, 1r) 6. clock synchronous delay line memory (2 addresses, 1w/1r) 7. clock synchronous fifo memory (2 addresses, 1w/1r) column type memory capacity word range bit range unit 8 128 to 512 k 32 to 4 k 4 to 128 bit 16 128 to 512 k 64 to 8 k 2 to 64 bit column type memory capacity word range bit range unit 8 512 to 32 k 32 to 1 k 16 to 32 bit 16 512 to 32 k 64 to 2 k 8 to 16 bit 32 512 to 32 k 128 to 4 k 4 to 8 bit column type memory capacity word range bit range unit 8 512 to 32 k 32 to 1 k 16 to 32 bit 16 512 to 32 k 64 to 2 k 8 to 16 bit 32 512 to 32 k 128 to 4 k 4 to 8 bit
CE77 series 6 absolute maximum ratings *1 : v ss = 0 v *2 : maximum output current wh ich can be supplied constantly. *3 : maximum supply current which can be supplied constantly. *4 : internal gate part in case of single power supply or dual power supply. *5 : i/o part in case 3.3 v i/f or 2. 5 v i/f is used by dual power supply. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. parameter symbol application rating unit min max power supply voltage* 1 v dd v dd = 1.4 v to 2.7 v ? 0.5 + 3.0* 4 v v dd = 2.7 v to 3.6 v + 4.0* 5 input voltage * 1 v i ? ? 0.5 v dd + 0.5 ( 3.0 v) * 4 v v dd + 0.5 ( 4.0 v) * 5 output voltage* 1 v o ? ? 0.5 v dd + 0.5 ( 3.0 v) * 4 v v dd + 0.5 ( 4.0 v) * 5 storage temperature tst ?? 55 + 125 c junction temperature tj ?? 40 + 125 c output current* 2 l type i o powerless type (i ol = 2 ma) ? 13 ma m type normal type (i ol = 4 ma) ? 13 h type power type (i ol = 8 ma) ? 13 v type high power type (i ol = 12 ma) ? 26 power-supply pin current * 3 i d per v dd , gnd pin ? 60 ma
CE77 series 7 recommended operating conditions 1. single power supply ? conditions: v dd = 2.5 v 0.2 v , v ss = 0 v ? conditions: v dd = 1.8 v 0.15 v , v ss = 0 v ? conditions: v dd = 1.5 v 0.1 v , v ss = 0 v parameter symbol value unit min typ max power supply voltage v dd 2.3 2.5 2.7 v ?h? level input voltage cmos normal v ih 1.7 ? v dd + 0.3 v cmos schmitt v dd 0.8 ?l? level input voltage cmos normal v il ? 0.3 ? + 0.7 v cmos schmitt v dd 0.2 junction temperature t j ? 40 ?+ 125 c parameter symbol value unit min typ max power supply voltage v ddi 1.65 1.8 1.95 v ?h? level input voltage cmos normal v ih v dd 0.65 ? v dd + 0.3 v cmos schmitt v dd 0.8 ?l? level input voltage cmos normal v il ? 0.3 ? v dd 0.35 v cmos schmitt v dd 0.2 junction temperature t j ? 40 ?+ 125 c parameter symbol value unit min typ max power supply voltage v ddi 1.4 1.5 1.6 v ?h? level input voltage cmos normal v ih v dd 0.7 ? v dd + 0.3 v cmos schmitt v dd 0.8 ?l? level input voltage cmos normal v il ? 0.3 ? v dd 0.3 v cmos schmitt v dd 0.2 junction temperature t j ? 40 ?+ 125 c
CE77 series 8 2. dual power supply ? conditions: v dde = 3.3 v 0.3 v / v ddi = 2.5 v 0.2 v , v ddi = 1.8 v 0.15 v , v ddi = 1.5 v 0.1 v , v ss = 0 v parameter symbol value unit min typ max power supply voltage v dde 3.0 3.3 3.6 v v ddi 1.4 ? 2.7 ?h? level input voltage 1.5 v cmos normal v ih v ddi 0.7 ? v ddi + 0.3 v 1.8 v cmos normal v ddi 0.65 2.5 v cmos normal 1.7 3.3 v cmos normal 2.0 v dde + 0.3 1.5 v cmos schmitt v ddi 0.8 v ddi + 0.3 1.8 v cmos schmitt 2.5 v cmos schmitt 3.3 v cmos schmitt v dde 0.8 v dde + 0.3 5 v tolerant 2.0 5.5 ?l? level input voltage 1.5 v cmos normal v il ? 0.3 ? v ddi 0.3 v 1.8 v cmos normal v ddi 0.35 2.5 v cmos normal + 0.7 3.3 v cmos normal + 0.8 1.5 v cmos schmitt v ddi 0.2 1.8 v cmos schmitt 2.5 v cmos schmitt 3.3 v cmos schmitt v dde 0.2 5 v tolerant + 0.8 junction temperature t j ? 40 ?+ 125 c
CE77 series 9 ? conditions: v dde = 2.5 v 0.2 v / v ddi = 1.8 v 0.15 v , v ddi = 1.5 v 0.1 v , v ss = 0 v warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit min typ max power supply voltage v dde 2.3 2.5 2.7 v v ddi 1.4 ? 1.95 ?h? level input voltage 1.5 v cmos normal v ih v ddi 0.7 ? v ddi + 0.3 v 1.8 v cmos normal v ddi 0.65 2.5 v cmos normal 1.7 v dde + 0.3 1.5 v cmos schmitt v ddi 0.8 v ddi + 0.3 1.8 v cmos schmitt 2.5 v cmos schmitt v dde 0.8 v dde + 0.3 ?l? level input voltage 1.5 v cmos normal v il ? 0.3 ? v ddi 0.3 v 1.8 v cmos normal v ddi 0.35 2.5 v cmos normal 0.7 1.5 v cmos schmitt v ddi 0.2 1.8 v cmos schmitt 2.5 v cmos schmitt v dde 0.2 junction temperature t j ? 40 ?+ 125 c
CE77 series 10 dc characteristics single power supply : v dd = 2.5 v ( standard ) *1 : when the memory is in a standb y mode and analog macro is in a power-d own mode. at both cases, conditions are v ih = v dd , v il = v ss , and t j = + 25 c. the above values may not be guar anteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : refer to ?(2) 2.5 v? in v-i characteristics. (v dd = 2.5 v 0.2 v, v ss = 0 v, t j = ? 40 c to + 125 c) parameter symbol conditions value unit min typ max power supply current* 1 i dds t2 ?? 0.1 ma t3, t4 ?? 0.2 t5 to t7 ?? 0.3 t8, t9 ?? 0.4 ta ?? 0.5 tb, tc ?? 0.6 td ?? 0.8 te ?? 1.0 tf ?? 1.1 tg ?? 1.3 ?h? level output voltage v oh i oh = ? 100 av dd ? 0.2 ? v dd v ?l? level output voltage v ol i ol = 100 a0 ? 0.2 v ?h? level output voltage v-i characteristics ? 2.5 v v dd = 2.5 v 0.2 v *2 ??? ?l? level output current v-i characteristics ? 2.5 v v dd = 2.5 v 0.2 v *2 ??? input leakage current i l ??? 5 a pull-up/pull-down resistance r p pull-up v il = 0 v pull-down v ih = v dd 10 25 120 k ?
CE77 series 11 single power supply : v dd = 1.8 v *1 : when the memory is in a standb y mode and analog macro is in a power-d own mode. at both cases, conditions are v ih = v dd , v il = v ss , and t j = + 25 c. the above values may not be guar anteed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : refer to ?(3) 1.8 v? in v-i characteristics. (v dd = 1.8 v 0.15 v, v ss = 0 v, t j = ? 40 c to + 125 c) parameter symbol conditions value unit min typ max power supply current* 1 i dds t2 ?? 0.1 ma t3, t4 ?? 0.2 t5 to t7 ?? 0.3 t8, t9 ?? 0.4 ta ?? 0.5 tb, tc ?? 0.6 td ?? 0.8 te ?? 1.0 tf ?? 1.1 tg ?? 1.3 ?h? level output voltage v oh i oh = ? 100 av dd ? 0.2 ? v dd v ?l? level output voltage v ol i ol = 100 a0 ? 0.2 v ?h? level output voltage v-i characteristics ? 1.8 v v dd = 1.8 v 0.15 v *2 ??? ?l? level output current v-i characteristics ? 1.8 v v dd = 1.8 v 0.15 v *2 ??? input leakage current i l ??? 5 a pull-up/pull-down resistance r p pull-up v il = 0 v pull-down v ih = v dd 10 40 120 k ?
CE77 series 12 single power supply : v dd = 1.5 v *1 : when the memory is in a standb y mode and analog macro is in a power-d own mode. at both cases, conditions are v ih = v dd , v il = v ss , and t j = + 25 c. the above values may not be guarant eed when the input buffer with a pull-up/pull-down resistor or a crystal oscillator buffer is used. *2 : refer to ?(4) 1.5 v? in v-i characteristics. (v dd = 1.5 v 0.1 v, v ss = 0 v, t j = ? 40 c to + 125 c) parameter symbol conditions value unit min typ max power supply current* 1 i dds t2 ?? 0.1 ma t3, t4 ?? 0.2 t5 to t7 ?? 0.3 t8, t9 ?? 0.4 ta ?? 0.5 tb, tc ?? 0.6 td ?? 0.8 te ?? 1.0 tf ?? 1.1 tg ?? 1.3 ?h? level output voltage v oh i oh = ? 100 av dd ? 0.2 ? v dd v ?l? level output voltage v ol i ol = 100 a0 ? 0.2 v ?h? level output voltage v-i characteristics ? 1.5 v v dd = 1.5 v 0.1 v *2 ??? ?l? level output current v-i characteristics ? 1.5 v v dd = 1.5 v 0.1 v *2 ??? input leakage current i l ??? 5 a pull-up/pull-down resistance r p pull-up v il = 0 v pull-down v ih = v dd 10 55 120 k ?
CE77 series 13 dual power supply : v dde = 3.3 v / v ddi = 2.5 v , 1.8 v , 1.5 v *1: when the memory is in a standby mode and analog macro is in a power-down mode. at both cases, conditions are v ih = v dd , v il = v ss , and t j = + 25 c. the above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a cr ystal oscillator buffer is used. *2: refer to ?(1) 3.3 v? in v-i characteristics. *3: refer to ?(2) 2.5 v? in v-i characteristics. *4: refer to ?(3) 1.8 v? in v-i characteristics?. *5: refer to ?(4) 1.5 v? in v-i characteristics. (v dde = 3.3 v 0.3 v/v ddi = 2.5 v 0.2 v, 1.8 v 0.15 v, 1.5 v 0.1 v, v ss = 0 v, t j = ? 40 c to + 125 c) parameter symbol conditions value unit min typ max power supply current* 1 i dds t2 ?? 0.1 ma t3, t4 ?? 0.2 t5 to t7 ?? 0.3 t8, t9 ?? 0.4 ta ?? 0.5 tb, tc ?? 0.6 td ?? 0.8 te ?? 1.0 tf ?? 1.1 tg ?? 1.3 ?h? level output voltage v oh4 3.3 v output i oh = ? 100 av dde ? 0.2 ? v dde v v oh3 2.5 v output i oh = ? 100 av ddi ? 0.2 ? v ddi v oh2 1.8 v output i oh = ? 100 av ddi ? 0.2 ? v ddi v oh1 1.5 v output i oh = ? 100 av ddi ? 0.2 ? v ddi ?l? level output voltage v ol4 3.3 v output i ol = 100 a0 ? 0.2 v v ol3 2.5 v output i ol = 100 a0 ? 0.2 v ol2 1.8 v output i ol = 100 a0 ? 0.2 v ol1 1.5 v output i ol = 100 a0 ? 0.2 ?h? level output v-i characteristics ? 3.3 v v dde = 3.3 v 0.3 v *2 ?? ? ? 2.5 v v ddi = 2.5 v 0.2 v *3 ?? ? 1.8 v v dde = 1.8 v 0.15 v *4 ?? ? 1.5 v v ddi = 1.5 v 0.1 v *5 ?? ?l? level output v-i characteristics ? 3.3 v v dde = 3.3 v 0.3 v *2 ?? ? ? 2.5 v v ddi = 2.5 v 0.2 v *3 ?? ? 1.8 v v dde = 1.8 v 0.15 v *4 ?? ? 1.5 v v ddi = 1.5 v 0.1 v *5 ?? input leakage current i l ??? 5 a pull-up/pull-down resistance r p 3.3 v pull-up v il = 0 pull-down v ih = v dde 10 25 70 k ? 2.5 v pull-up v il = 0 pull-down v ih = v ddi 10 25 120 1.8 v pull-up v il = 0 pull-down v ih = v ddi 10 40 120 1.5 v pull-up v il = 0 pull-down v ih = v ddi 10 55 120
CE77 series 14 dual power supply : v dde = 2.5 v / v ddi = 2.5 v , 1.8 v , 1.5 v *1: when the memory is in a standby mode and analog macro is in a power-down mode. at both cases, conditions are v ih = v dd , v il = v ss , and t j = + 25 c. the above values may not be guaranteed when the input buffer with a pull-up/pull-down resistor or a cr ystal oscillator buffer is used. *2: refer to ?(2) 2.5 v? in v-i characteristics. *3: refer to ?(3) 1.8 v? in v-i characteristics?. *4: refer to ?(4) 1.5 v? in v-i characteristics. (v dde = 2.5 v 0.2 v/v ddi = 1.8 v 0.15 v, 1.5 v 0.1 v, v ss = 0 v, t j = ? 40 c to + 125 c) parameter symbol conditions value unit min typ max power supply current* 1 i dds t2 ?? 0.1 ma t3, t4 ?? 0.2 t5 to t7 ?? 0.3 t8, t9 ?? 0.4 ta ?? 0.5 tb, tc ?? 0.6 td ?? 0.8 te ?? 1.0 tf ?? 1.1 tg ?? 1.3 ?h? level output voltage v oh3 2.5 v output i oh = ? 100 av dde ? 0.2 ? v dde v v oh2 1.8 v output i oh = ? 100 av ddi ? 0.2 ? v ddi v oh1 1.5 v output i oh = ? 100 av ddi ? 0.2 ? v ddi ?l? level output voltage v ol3 2.5 v output i ol = 100 a0 ? 0.2 v v ol2 1.8 v output i ol = 100 a0 ? 0.2 v ol1 1.5 v output i ol = 100 a0 ? 0.2 ?h? level output v-i characteristics ? 2.5 v v dde = 2.5 v 0.2 v *2 ?? ? ? 1.8 v v ddi = 1.8 v 0.15 v *3 ?? ? 1.5 v v ddi = 1.5 v 0.1 v *4 ?? ?l? level output v-i characteristics ? 2.5 v v dde = 2.5 v 0.2 v *2 ?? ? ? 1.8 v v ddi = 1.8 v 0.15 v *3 ?? ? 1.5 v v ddi = 1.5 v 0.1 v *4 ?? input leakage current i l ??? 5 a pull-up/pull-down resistance r p 2.5 v pull-up v il = 0 pull-down v ih = v dde 10 25 120 k ? 1.8 v pull-up v il = 0 pull-down v ih = v ddi 10 40 120 1.5 v pull-up v il = 0 pull-down v ih = v ddi 10 55 120
CE77 series 15 v-i characteristics (1) 3.3 v 3.3 v normal i/o v-i characteristics [ condition : v dd = 3.0 v ] 3.3 v normal i/o v-i characteristics [ condition : v dd = 3.3 v ] 3.3 v normal i/o v-i characteristics [ condition : v dd = 3.6 v ] 0.0 ? 10.0 ? 20.0 ? 30.0 ? 40.0 ? 50.0 0.0 1.0 2.0 v oh (v) 3.0 40.0 30.0 20.0 10.0 0.0 0.0 1.0 2.0 v ol (v) 3.0 ?h? level output v-i characteristics (v dd = 3.0 v) 3.0 v normal i/o v oh -i oh (min) < v dd = 3.0 v > ?l? level output v-i characteristics (v dd = 3.0 v) 3.0 v normal i/o v ol -i ol (min) < v dd = 3.0 v > l type m type h type v type l type m type h type v type i oh (min) (ma) i ol (min) (ma) 0.0 ? 10.0 ? 20.0 ? 30.0 ? 40.0 ? 50.0 0.0 1.0 2.0 v oh (v) 3.0 40.0 30.0 20.0 10.0 0.0 0.0 1.0 2.0 v ol (v) 3.0 ?h? level output v-i characteristics (v dd = 3.3 v) 3.3 v normal i/o v oh -i oh (min) < v dd = 3.3 v > ?l? level output v-i characteristics (v dd = 3.3 v) 3.3 v normal i/o v ol -i ol (min) < v dd = 3.3 v > l type m type h type v type l type m type h type v type i oh (min) (ma) i ol (min) (ma) 0.0 ? 10.0 ? 20.0 ? 30.0 ? 40.0 ? 50.0 0.0 1.0 2.0 v oh (v) 3.0 40.0 30.0 20.0 10.0 0.0 0.0 1.0 2.0 v ol (v) 3.0 ?h? level output v-i characteristics (v dd = 3.6 v) 3.3 v normal i/o v oh -i oh (min) < v dd = 3.6 v > ?l? level output v-i characteristics (v dd = 3.6 v) 3.3 v normal i/o v ol -i ol (min) < v dd = 3.6 v > l type m type h type v type l type m type h type v type i oh (min) (ma) i ol (min) (ma)
CE77 series 16 (2) 2.5 v 2.5 v normal i/o v-i characteristics [ condition : v dd = 2.3 v ] 2.5 v normal i/o v-i characteristics [ condition : v dd = 2.5 v ] 2.5 v normal i/o v-i characteristics [ condition : v dd = 2.7 v ] 0.0 ? 10.0 ? 20.0 ? 30.0 0.0 1.0 v oh (v) 2.0 3.0 30.0 20.0 10.0 0.0 0.0 1.0 v ol (v) 2.0 3.0 ?h? level output v-i characteristics (v dd = 2.3 v) 2.5 v normal i/o v oh -i oh (min) < v dd = 2.3 v > ?l? level output v-i characteristics (v dd = 2.3 v) 2.5 v normal i/o v ol -i ol (min) < v dd = 2.3 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma) 0.0 ? 10.0 ? 20.0 ? 30.0 0.0 1.0 v oh (v) 2.0 3.0 30.0 20.0 10.0 0.0 0.0 1.0 v ol (v) 2.0 3.0 ?h? level output v-i characteristics (v dd = 2.5 v) 2.5 v normal i/o v oh -i oh (min) < v dd = 2.5 v > ?l? level output v-i characteristics (v dd = 2.5 v) 2.5 v normal i/o v ol -i ol (min) < v dd = 2.5 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma) 0.0 ? 10.0 ? 20.0 ? 30.0 ? 40.0 0.0 1.0 v oh (v) 2.0 3.0 30.0 20.0 10.0 0.0 0.0 1.0 v ol (v) 2.0 3.0 ?h? level output v-i characteristics (v dd = 2.7 v) 2.5 v normal i/o v oh -i oh (min) < v dd = 2.7 v > ?l? level output v-i characteristics (v dd = 2.7 v) 2.5 v normal i/o v ol -i ol (min) < v dd = 2.7 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma)
CE77 series 17 (3) 1.8 v 1.8 v normal i/o v-i characteristics [ condition : v dd = 1.65 v ] 1.8 v normal i/o v-i characteristics [ condition : v dd = 1.8 v ] 1.8 v normal i/o v-i characteristics [ condition : v dd = 1.95 v ] 0.0 ? 10.0 ? 20.0 0.0 1.0 v oh (v) 2.0 20.0 10.0 0.0 0.0 1.0 v ol (v) 2.0 ?h? level output v-i characteristics (v dd = 1.65 v) 1.8 v normal i/o v oh -i oh (min) < v dd = 1.65 v > ?l? level output v-i characteristics (v dd = 1.65 v) 1.8 v normal i/o v ol -i ol (min) < v dd = 1.65 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma) 0.0 ? 10.0 ? 20.0 0.0 1.0 v oh (v) 2.0 20.0 10.0 0.0 0.0 1.0 v ol (v) 2.0 ?h? level output v-i characteristics (v dd = 1.8 v) 1.8 v normal i/o v oh -i oh (min) < v dd = 1.8 v > ?l? level output v-i characteristics (v dd = 1.8 v) 1.8 v normal i/o v ol -i ol (min) < v dd = 1.8 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma) 0.0 ? 10.0 ? 20.0 ? 30.0 0.0 1.0 v oh (v) 2.0 20.0 10.0 0.0 0.0 1.0 v ol (v) 2.0 ?h? level output v-i characteristics (v dd = 1.95 v) 1.8 v normal i/o v oh -i oh (min) < v dd = 1.95 v > ?l? level output v-i characteristics (v dd = 1.95 v) 1.8 v normal i/o v ol -i ol (min) < v dd = 1.95 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma)
CE77 series 18 (4) 1.5 v 1.5 v normal i/o v-i characteristics [ condition : v dd = 1.4 v ] 1.5 v normal i/o v-i characteristics [ condition : v dd = 1.5 v ] 1.5 v normal i/o v-i characteristics [ condition : v dd = 1.6 v ] 0.0 ? 5.0 ? 10.0 ? 15.0 0.0 0.5 1.0 v oh (v) 1.5 15.0 10.0 5.0 0.0 0.0 0.5 1.0 v ol (v) 1.5 ?h? level output v-i characteristics (v dd = 1.4 v) 1.5 v normal i/o v oh -i oh (min) < v dd = 1.4 v > ?l? level output v-i characteristics (v dd = 1.4 v) 1.5 v normal i/o v ol -i ol (min) < v dd = 1.4 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma) 0.0 ? 5.0 ? 10.0 ? 15.0 0.0 0.5 1.0 v oh (v) 1.5 15.0 10.0 5.0 0.0 0.0 0.5 1.0 v ol (v) 1.5 ?h? level output v-i characteristics (v dd = 1.5 v) 1.5 v normal i/o v oh -i oh (min) < v dd = 1.5 v > ?l? level output v-i characteristics (v dd = 1.5 v) 1.5 v normal i/o v ol -i ol (min) < v dd = 1.5 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma) 0.0 ? 5.0 ? 10.0 ? 15.0 ? 20.0 0.0 0.5 1.0 v oh (v) 1.5 15.0 10.0 5.0 0.0 0.0 0.5 1.0 v ol (v) 1.5 ?h? level output v-i characteristics (v dd = 1.6 v) 1.5 v normal i/o v oh -i oh (min) < v dd = 1.6 v > ?l? level output v-i characteristics (v dd = 1.6 v) 1.5 v normal i/o v ol -i ol (min) < v dd = 1.6 v > l type m type h type v type i oh (min) (ma) l type m type h type v type i ol (min) (ma)
CE77 series 19 ac characteristics *1 : delay time = propagation delay time, enable time, disable time *2 : ?typ? is calculated fr om the cell specification. *3 : measurement condition note : tpd max is calculated according to the maximum junction temperature (t j ) . input/output capacitance design method linking a floor plan tool and a logic synthesis tool enable s automatic circuit optimization using floor plan infor- mation. in addition, cddm (clock driven design method) clock tree synthesis tools using floor plan information is also available. using floor plan information at a pr e-layout stage prevents major problems with setup and hold timings which can occur after layout. using a hierarchical layout method to support larger-scale circuit design considerably shortens the overall design cycle time. (v dd = 1.8 v 0.15 v, v ss = 0 v, t j = ? 40 c to + 125 c) parameter symbol value unit min typ max delay time t pd * 1 typ* 2 tmin* 3 typ* 2 ttyp* 3 typ* 2 tmax* 3 ns measurement condition tmin ttyp tmax v dd = 2.5v 0.2 v, v ss = 0 v, t j = ? 40 c to + 125 c 0.60 1.00 1.64 v dd = 1.8v 0.15 v, v ss = 0 v, t j = ? 40 c to + 125 c 0.84 1.57 2.84 v dd = 1.5v 0.1 v, v ss = 0 v, t j = ? 40 c to + 125 c 1.14 2.22 4.09 (f = 1 mhz, v dd = v i = 0 v, tj = + 25 c) parameter symbol value unit input pin c in max 16 pf output pin c out max 16 pf input/output capacitance c i / o max 16 pf
CE77 series 20 the number of gates used and packages 1. counting the number of the gates used evaluation of the basic cell count used has revealed some problems including the circuit complexities, difference of the utilization depending on the circuit design scheme (whether it is designed with the logic synthesis) or being unable to achieve the minimum layout with the logically synthesized circuit. to cope with those problems, fujitsu developed the area as a criteria where the circuit size and the layout feasibility is determined. the area is a basic cell concei ved from the viewpoint of congestion of the wiring; it has been calculated from the actual basic cell count and pin count in units of bc. estimate method for the frame include the conventio nal one by the basic cell count and the one by the area for more detailed estimate. hard macro basic cell count and area count for unit cell, i/ o buffer cell or compiled cell are listed in the respective cell characteristic table. 2. packages the table below lists the package types availa ble and the reference number of gates used. consult fujitsu for the combination of each package and the availability. CE77 (v-frame) note : the packages that can be used depend on the circ uit configuration. for details, contact fujitsu. 176 20 8 240 s q f p 0.5 0.5 0.5 274k 8 0 3 k 965k 20 8 240 256 3 04 h q f p 0.5 0.5 0.4 0.5 1776k 2276k 1776k 256 p b g a 1.27 61 8 k 712 8 k 0k 1000k 2000k 3 000k 4000k 5000k 6000k 7000k 8 000k~ p a ck a ge & pin co u nt pin pitch (mm)
CE77 series 21 CE77 (t-frame) note : the packages that can be used depend on the circ uit configuration. for details, contact fujitsu. 144 176 20 8 256 l q f p 0.5 0.5 0.5 0.4 1241k 744k 1 3 75k 2109k 20 8 240 256 3 04 h q f p 0.5 0.5 0.4 0.5 267 8 k 2109k 2109k 45 38 k 144 176 224 22 8 f b g a 0. 8 0. 8 0. 8 0.75 461k 646k 1 3 75k 2109k 256 3 52 420 p b g a 1.27 1.27 1.27 2109k 267 8 k 3 7 8 9k 0k 500k 1000k 1500k 2000k 2500k 3 000k 3 500k 4000k 4500k 5000k 5500k p a ck a ge & pin co u nt pin pitch (mm)
CE77 series 22 basic characteristics (continued) 2.0 1.5 1.0 0.5 0.0 0.6 0.7 0.8 0.9 1.0 1.1 v dd = 1.4 v v dd = 1.5 v v dd = 1.6 v v dd = 1.8 v v dd = 1.95 v v in (v) v out (v) v dd = 2.3 v v dd = 2.5 v v dd = 2.7 v 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.00 1.05 1.10 1.15 1.20 v in (v) v out (v) 1.25 1.30 1.35 1.40 v in (v) v out (v) v dd = 1.95 v v dd = 1.8 v v dd = 1.6 v v dd = 1.5 v v dd = 1.4 v v dd = 1.4 v v dd = 1.5 v v dd = 1.6 v v dd = 1.8 v v dd = 1.95 v 2.0 1.5 1.0 0.5 0.0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v in (v) v out (v) v dd = 2.7 v v dd = 2.5 v v dd = 2.3 v v dd = 2.3 v v dd = 2.5 v v dd = 2.7 v 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 transfer characteristics (typical cmos input buffer) 1 transfer characteristics (typical cmos input buffer) 2 transfer characteristics (typ ical schmitt input buffer) 1 transfer characteristics (typical schmitt input buffer) 2
CE77 series 23 (continued) 3.00 2.50 2.00 1.50 1.00 0.50 0.00 ? 0.50 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 v dde = 3.0 v v dde = 3.3 v v dde = 3.6 v v in (v) v out (v) 3.00 2.50 2.00 1.50 1.00 0.50 0.00 0.80 1.30 1.80 2.30 v dde = 3.0 v v dde = 3.6 v v dde = 3.3 v v dde = 3.0 v v dde = 3.6 v v dde = 3.3 v v in (v) v out (v) transfer characteristics (3.3 v normal cmos input buffer v ddi = 2.5 v) transfer characteristics (3.3 v normal schmitt input buffer v ddi = 2.5 v)
CE77 series f0701 fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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